CAMPBELL, Calif., Oct. 17, 2023 (GLOBE NEWSWIRE) -- Arteris, Inc. (Nasdaq: AIP), a leading provider of system IP which accelerates system-on-chip (SoC) creation and Fraunhofer IESE, one of the leading research institutes in the area of software and systems engineering methods, today announced they have partnered to enable interoperability between Arteris' FlexNoC and Ncore network-on-chip (NoC) development environment and Fraunhofer IESE's DRAM subsystem design space exploration framework.

加利福尼亚州坎贝尔，2023年10月17日（GLOBE NEWSWIRE）-Arteris，Inc。（纳斯达克股票代码：AIP），系统IP的领先提供商，加速系统芯片（SoC）的创建和Fraunhofer IESE，其中之一软件和系统工程方法领域的领先研究机构，今天宣布他们已经合作实现Arteris的FlexNoC和Ncore片上网络（NoC）开发环境与Fraunhofer IESE的DRAM子系统设计空间探索框架之间的互操作性。

The interoperability will improve performance, reduce cost and accelerate the schedule of advanced DRAM-centric NoC development for mutual customers. 'Early, accurate modeling of the characteristics of the latest DRAM architectures is a critical component to arrive at optimal power-optimized SoC architectures,' said Professor Dr.

互操作性将提高性能，降低成本，加快面向共同客户的以DRAM为中心的先进NoC开发时间表早期，对最新DRAM架构特性的准确建模是获得最佳功率优化SoC架构的关键组件，“博士说。

Matthias Jung, an expert in virtual engineering at Fraunhofer IESE. 'By enabling interoperability and integration between Arteris' FlexNoC and Ncore with DRAMSys4.0, our customers can understand the impact of advanced DRAM technology on NoC performance and power consumption at the earliest project stages, avoiding surprises leading to architecture redesigns later in the project cycle.' DRAM performance is critical for today's advanced AI/ML architectures due to requirements on efficiency of data movement, computation, AI model complexity, real-time inference and energy consumption.

Fraunhofer IESE虚拟工程专家Matthias Jung通过实现Arteris的FlexNoC和Ncore与DRAMSys4.0之间的互操作性和集成，我们的客户可以在项目早期阶段了解先进DRAM技术对NoC性能和功耗的影响，避免意外导致项目周期后期架构重新设计由于对数据移动，计算，AI模型复杂性，实时推理和能耗效率的要求，DRAM性能对于当今先进的AI/ML体系结构至关重要。

While models of memory controllers impact memory access mapping, command generation and timing control, memory organization, configuration and error correction, memory models also manage data storage, access, retrieval, refresh and retention. DRAMSys consists of models that reflect the DRAM functionality, power, and temperature.

虽然存储器控制器模型影响存储器访问映射，命令生成和时序控制，存储器组织，配置和纠错，但存储器模型还管理数据存储，访问，检索，刷新和保留。DRAMSys由反映DRAM功能，功率和温度的模型组成。

It allows system designers to analyze the limiting .

它允许系统设计者分析限制。